1. Field of Invention
The present invention relates to a sample-and-hold (S/H) device. More particularly, the present invention relates to a sample-and-hold device having a plurality of input stages.
2. Description of Related Art
FIG. 1 is a circuit diagram illustrating a conventional sample-and-hold device having an input stage. Referring to FIG. 1, the sample-and-hold device 100 includes switches S1˜S4, capacitors C1˜C2 and an amplifier 110. The amplifier 100 includes, for example, an input stage 120 and an output stage 140, in which the input stage 120 includes a differential input unit 121 and a bias current source I1.
The switches S1˜S4 are controlled by a plurality of non-overlapping clock signals so as to determine whether the switches should be turned on or turned off. During the first period, switches S1 and S4 are turned on while switches S2 and S3 are turned off, the sample-and-hold device 100 stores the input voltage Vin in the capacitor C1, and meanwhile, obtains the output voltage Vout from the electric charge stored in the capacitor C2. Then during the second period, switches S1 and S4 are turned off and switches S2 and S3 are turned on, the sample-and-hold device 100 obtains the output voltage Vout from the electric charge stored in the capacitor C1 and stores the next input voltage Vin in the capacitor C2.
However, in the input stage 120 of the amplifier 110, there will be a parasitic capacitor at its positive input terminal, thus the output voltage Vout of the amplifier 110 may be distorted by the sample-and-hold device 100 due to charge sharing.
For example, during the first period, switch S1 is turned on and switch S3 is turned off, thus the capacitor C1 stores an amount of electric charge C1Vin, in which C1 represents the capacitance of the capacitor C1. During the second period, switch S1 is turned off and switch S3 is turned on, at this point, part of the electric charge stored in the capacitor C1 flows to the parasitic capacitor at the positive input terminal of the input stage 120 due to charge sharing. Therefore, the voltage level supplied to the positive input terminal of the input stage 120 in fact is distorted to C1Vin/(C1+CP1), in which CP1 represents the capacitance of the parasitic capacitor at the positive input terminal of the input stage 120. The voltage level distortion at the positive input terminal of the input stage will cause the distortion of the output voltage Vout of the amplifier 110. The same problem may as well occur in the capacitor C2 and the input stage 120 which has also charge sharing during the first period while switch S4 is turned on and switch S2 is turned off.